In a prior art computer with microprogramming, the control section of such a computer generally is provided with an autonomous read-only storage. Each time a program instruction begins, the control unit generates an address to its read-only storage derived from the function or operation code of the instruction. This address locates what may be the first of a series of words which supply the control signals to the computer for carrying out the particular instruction being processed. Each instruction in effect generates a transfer to a microsubroutine associated with it, and the resultant step-by-step operation of the machine corresponds to the execution of a program on a very detailed level.
In such a computer in the prior art, program instructions generally comprise an operation code, i.e., the opcode, together with information relative to the location of the operands, that is, the data to be operated on. These operands sometimes may also have additional operational information. The length of the program instructions may be relatively long or relatively short depending on the quantity of data involved. The operating codes generally indicate the operation to be performed. Once the length of the operating code is established, it is possible to have only a certain fixed set of different operating codes and related program instructions. However, not all the operating codes which may theoretically be expressed with a certain number of bits, i.e., operating codes within the fixed set, are used to characterize program instructions for which the computer is provided with microprogramming resources. Generally, only a part or subset is used, and thus programming efficiency is degraded.
Also in a prior art computer, the memory of the computer provides the largest hardware cost. Therefore, the key to hardware speed and minimum size lies in efficient use of the memory. Fixed instruction length computers require the same number of bits for each instruction word regardless of the simplicity or complexity of the operation to be executed. As an example, many bits can be wasted in instructions which specify simple operations, while many instructions can be wasted in complex operations where an instruction's capability is limited by its length. Therefore, it is desired to design a computer with an instruction set which can perform all applications most efficiently.
To increase the efficiency of microprogramming in the prior art, the concept of optimizing compilers is used and implemented (1) to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space and (2) to make the instruction cycle time as fast as the technology would allow. Computers having such optimized compilers are designed to have fewer instructions than those in the prior art, and what few instructions they do have are simple and would generally execute in one cycle. Such computers have been aptly named reduced instruction set computers (RISCs). Instructions that are part of a reduced instruction set in a RISC machine and that provide increased efficiency in a novel way have been invented and are described herein.
Specifically, many programs have methods to evaluate a condition and to store the results of the evaluation into a Boolean variable. Most computer instruction sets in the prior art, however, can only use a condition, which is usually the result of a comparison, to affect a branching decision and not to materialize the condition as a value.
An example of one of these prior art instruction sets is an instruction set which compiles a code that uses the condition to branch around the code that sets or clears bits. This instruction set is generally slow and involves conditional branches which can flush the pipeline of high-performance processors.
Another example is a prior art instruction set which implements special instructions which put a bit which is the condition value into a register. This instruction set involves waiting until the condition is selected and resolved before storing the result. This operation, which uses different timing, is slower than selecting and storing the result of an arithmetic operation.
In accordance with the preferred embodiment of the invention, an instruction set uses a two instruction sequence to store the result of a comparison. The two instruction sequence uses no branch instructions, and does not wait for condition resolution before storing results. It can also implement slightly more general operations than simply storing a zero or one value of a comparison.
Basically, the novel instruction set compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set also conditionally nullifies the instruction following it.